View ADS850_9039479.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features self-calibrating high sfdr: 85db at nyquist high snr: 76db low power: 250mw differential or single-ended inputs +3v/+5v logic i/o compatible flexible input range over-range indicator internal or external reference applications if and baseband digitization ccd imaging scanners test instrumentation ir imaging description the ADS850 is a high dynamic range, 14-bit analog-to-digital converter (adc) that utilizes a fully differential input, allowing for either single-ended or differential input interface over varying input spans. this converter features digital error correction tech- niques ensuring 14-bit linearity and a calibration procedure that corrects for capacitor and gain mismatches. the ADS850 also includes a high-bandwidth track-and-hold that provides excellent spurious performance up to and beyond the nyquist rate. the ADS850 provides an internal reference that can be pro- grammed for a 2vp-p input range for the best spurious perfor- mance and ease of driving. alternatively, the 4vp-p input range can be used for the lowest input referred noise, offering superior signal-to-noise performance for imaging applications. there is also the capability to set the range between 2vp-p and 4vp-p, or to use an external reference. the ADS850 also provides an over-range indicator flag to indicate if the input has exceeded the full-scale input range of the converter. the low distortion and high signal-to-noise performance pro- vide the extra margin needed for communications, imaging, and test instrumentation applications. the ADS850 is available in a tqfp-48 package. 14-bit pipelined adc core reference and mode select reference ladder and driver timing circuitry error correction logic and calibration circuitry 3-state outputs t&h d0 d13 clk +v s ADS850 vdrv oe sel refb v ref reft in v in in (opt.) cm ovr 14-bit, 10msps self-calibrating analog-to-digital converter ADS850 sbas154c ?october 2000 ?revised october 2002 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ?2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ADS850
ADS850 sbas154c 2 www.ti.com electrical characteristics at t a = full specified temperature range, v s = +5v, specified differential input range = 1.5v to 3.5v, internal reference input, sampling rate = 10msps after calibration, and v ref = 2v, unless otherwise specified. ADS850y parameter conditions min typ max units resolution 14 bits specified temperature range ?0 to +85 c conversion characteristics sample rate 10k 10m samples/s data latency 7 clk cycles analog input single-ended input range v ref = 1.0 1.5 3.5 v v ref = 2.0 0.5 4.5 v differential input range v ref = 2.0 1.5 3.5 v common-mode voltage 2.5 v 1v input capacitance 20 pf analog input bandwidth ?dbfs input 270 mhz dynamic characteristics differential linearity error (largest code error) f = 4.8mhz 0.75 1.0 lsb no missing codes tested spurious-free dynamic range (1) f = 4.8mhz (?db input) 4vp-p 75 85 dbfs (2) f = 4.8mhz (?db input) 2vp-p 82 dbfs signal-to-noise ratio (snr) f = 4.8mhz (?db input) 4vp-p 71 76 dbfs f = 4.8mhz (?db input) 2vp-p 73 dbfs signal-to-(noise + distortion) (sinad) f = 4.8mhz (?db input) 4vp-p 70 75 dbfs f = 4.8mhz (?db input) 2vp-p 72 dbfs effective number of bits at 4.8mhz (3) 12.2 bits integral nonlinearity error f = 4.8mhz 2.5 5.0 lsb aperture delay time 1ns aperture jitter 4 ps rms overvoltage recovery time 1.5 ?fs input 2 ns full-scale step acquisition time 50 ns +v s ....................................................................................................... +6v analog input ........................................................... (?.3v) to (+v s +0.3v) logic input ............................................................. (?.3v) to (+v s +0.3v) case temperature ......................................................................... +100 c junction temperature .................................................................... +150 c storage temperature ..................................................................... +150 c absolute maximum ratings (1) electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. product demo board ADS850y ADS850y-evm demo board ordering information specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity ADS850y tqfp-48 pfb ?0 c to +85 c ADS850y ADS850y/250 tape and reel, 250 " """" ADS850y/2k tape and reel, 2000 package/ordering information note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. note: (1) stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability.
ADS850 sbas154c 3 www.ti.com electrical characteristics (cont.) at t a = full specified temperature range, v s = +5v, specified differential input range = 1.5v to 3.5v, internal reference input, sampling rate = 10msps after calibration, and v ref = 2v, unless otherwise specified. ADS850y parameter conditions min typ max units digital inputs logic family +3v/+5v logic compatible cmos convert command start conversion rising edge of convert clock high level input current (v in = 5v) (4) 100 a low level input current (v in = 0v) 10 a high level input voltage +2.0 v low level input voltage +1.0 v input capacitance 5pf digital outputs logic family +3v/+5v logic compatible cmos v logic coding straight offset binary low output voltage (i ol = 50 a) 0.1 v low output voltage (i ol = 1.6ma) 0.4 v high output voltage (i oh = 50 a) +4.5 v high output voltage (i oh = 0.5ma) +2.4 v 3-state enable time oe = low 20 40 ns 3-state disable time oe = high 2 10 ns output capacitance 5pf accuracy (4vp-p input range) zero error (referred to ?s) at 25 c 0.2 %fs zero error drift (referred to ?s) 5 ppm/ c gain error (5) at 25 c 0.7 %fs gain error drift (5) 15 ppm/ c gain error (6) at 25 c 0.042 %fs gain error drift (6) 15 ppm/ c power-supply rejection of gain ? v s = 5% 82 db reference input resistance 1.6 k ? internal voltage reference tolerance (v ref = 2.0v) (7) at 25 c 13.5mv mv internal voltage reference tolerance (v ref = 1.0v) (7) at 25 c 6mv mv power-supply requirements supply voltage: +v s operating +4.7 +5.0 +5.3 v supply voltage: vdrv operating +2.7 +5.3 v supply current: +i s operating 53 ma power dissipation vdrv = 3v external reference 240 mw vdrv = 5v external reference 245 mw vdrv = 3v internal reference 250 275 mw vdrv = 5v internal reference 255 mw power-down 20 mw thermal resistance, ja tqfp-48 56.5 c/w notes: (1) spurious-free dynamic range refers to the difference in magnitude between the fundamental and the next largest harmo nic. (2) dbfs means db relative to full scale. (3) effective number of bits (enob) is defined by (sinad ?1.76)/6.02. (4) internal 50k ? pull-down resistor. (5) includes internal reference. (6) excludes internal reference. (7) typical reference tolerance based on 1 sigma of distribution.
ADS850 sbas154c 4 www.ti.com pin configuration 1+v s +5v supply 2+v s +5v supply 3+v s +5v supply 4+v s +5v supply 5 gnd ground 6 i clk convert clock input 7 nc no connection 8 i mem_rst memory reset. when pulsed high, resets memory to zero. not intended as a function pin, so should be perma- nently tied to ground. 9 i cal when pulsed high, puts adc into cali- bration mode (2 clock cycles). 10 ovr over range indicator 11 cal_busy indicates in calibration mode. 12 o b1 (msb) data bit 1 (d13) (msb) 13 o b2 data bit 2 (d12) 14 o b3 data bit 3 (d11) 15 o b4 data bit 4 (d10) 16 o b5 data bit 5 (d9) 17 o b6 data bit 6 (d8) 18 o b7 data bit 7 (d7) 19 o b8 data bit 8 (d6) 20 o b9 data bit 9 (d5) 21 o b10 data bit 10 (d4) 22 o b11 data bit 11 (d3) 23 o b12 data bit 12 (d2) 24 o b13 data bit 13 (d1) 25 o b14 (lsb) data bit 14 (d0) (lsb) 26 vdrv output driver voltage 27 gnd ground 28 i oe output enable: hi = high impedance; lo = normal operation (50k ? internal pull-down resistor) 29 i pd power down: hi = power down; lo = normal operation (50k ? internal pull-down resistor) 30 i btc hi = binary twos complement (btc); lo = straight offset binary (sob) 31 gnd ground 32 gnd ground 33 sel input range select 34 i/o v ref reference voltage select 35 gnd ground 36 +v s +5v supply 37 cbp2 calibration reference bypass 2 (0.1 f ce- ramic capacitor recommended for decou- pling.) 38 gnd ground 39 i/o refb bottom reference voltage bypass 40 o cm common-mode voltage (mid-scale). not in- tended for driving a load. 41 i/o reft top reference voltage bypass 42 gnd ground 43 cbp1 calibration reference bypass 1 (0.1 f ce- ramic capacitor recommended for decou- pling.) 44 gnd ground 45 i in complementary analog input (? 46 gnd ground 47 i in analog input (+) 48 gnd ground pin i/o designator description pin i/o designator description pin descriptions top view tqfp 36 35 34 33 32 31 30 29 28 27 26 25 +v s gnd v ref sel gnd gnd btc pd oe gnd vdrv b14 (lsb) gnd in gnd in gnd cbp1 gnd reft cm refb gnd cbp2 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 1 2 3 4 5 6 7 8 9 10 11 12 +v s +v s +v s +v s gnd clk nc mem_rst cal ovr cal_busy b1 (msb) 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 ADS850y
ADS850 sbas154c 5 www.ti.com timing diagrams symbol description min typ max units t conv convert clock period 100 100 sns t l clock pulse low 48 t conv /2 ns t h clock pulse high 48 t conv /2 ns t d aperture delay 2 ns t 1 data hold time, c l = 0pf 3.9 ns t 2 new data delay time, c l = 15pf max 12 ns 7 clock cycles data invalid t d t l t h t conv n 7n 6n 5n 4n 3n 2n 1n data out clk analog in n t 2 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 t 1 t p cal clk busy data out 32,768 cycles data invalid calibrated adc t p = 2 t conv data valid 7 clock cycles timing diagram 1. pipeline delay timing. timing diagram 2. power-on calibration mode timing. timing diagram 3. calibration-on-demand mode timing. timing diagram 4. reset mode timing. v ref clk busy data out t s t s = time for reference to settle (< 200ms). 32,768 cycles delay time = 2 21 clocks 7 clock cycles data invalid t p rst clk data out uncalibrated adc
ADS850 sbas154c 6 www.ti.com typical characteristics at t a = full specified temperature range, v s = +5v, specified input range = 1.5v to 3.5v, differential internal reference input and sampling rate = 10msps after calibratio n, v ref = 2v, 1db input, unless otherwise specified. spectral performance (4vp-p, differential, f in = 4.8mhz) amplitude (db) 0 10 30 50 70 90 110 130 01 0.5 2 1.5 3 2.5 4 3.5 frequency (mhz) 5 4.5 sfdr = 89dbfs snr = 76dbfs spectral performance (2vp-p, differential, f in = 4.8mhz) amplitude (db) 0 10 30 50 70 90 110 130 01 2 0.5 1.5 2.5 3.5 34.5 4 frequency (mhz) 5 sfdr = 88dbfs snr = 73dbfs spectral performance (2vp-p, single-ended, f in = 4.8mhz) amplitude (db) 0 10 30 50 70 90 110 130 01 0.5 2 1.5 3 3.5 2.5 4 4.5 frequency (mhz) 5 sfdr = 85dbfs snr = 73dbfs spectral performance (4vp-p, differential, f in = 1mhz) amplitude (db) 0 10 30 50 70 90 110 130 01 2 0.5 1.5 2.5 3.5 3 4.5 4 frequency (mhz) 5 sfdr = 82dbfs snr = 76dbfs spectral performance (2vp-p, single-ended, f in = 1mhz) amplitude (db) 0 10 30 50 70 90 110 130 01 2 0.5 1.5 2.5 3.5 3 4.5 4 frequency (mhz) 5 sfdr = 87dbfs snr = 73dbfs undersampling (differential, 4vp-p) amplitude (dbfs) 0 20 40 60 80 100 120 140 0 0.4 0.8 0.2 0.6 1 1.4 1.2 frequency (mhz) 1.6 f s = 3.2mhz f in = 10mhz sfdr = 87dbfs snr = 73dbfs
ADS850 sbas154c 7 www.ti.com typical characteristics (cont.) at t a = full specified temperature range, v s = +5v, specified input range = 1.5v to 3.5v, differential internal reference input and sampling rate = 10msps after calibratio n, v ref = 2v, 1db input, unless otherwise specified. differential linearity error dle (lsb) 1 0.75 0.5 0.25 0 0.25 0.5 0.75 1 0 4096 8192 12288 code 16384 f in = 4.8mhz integral linearity error ile (lsb) 4 3 2 1 0 1 2 3 4 0 4096 8192 12288 code 16384 f in = 4.8mhz output noise histogram (4vp-p) counts 9k 8k 7k 6k 5k 4k 3k 2k 1k 0k n 1 n n + 1 codes 95 90 85 80 sfdr vs temperature sfdr (db) 45 25 51535557595 temperature ( c) f in = 500khz f in = 4.8mhz 85 80 75 70 sinad vs temperature sinad (db) 45 25 51535557595 temperature ( c) f in = 500khz f in = 4.8mhz 110 100 90 80 70 60 50 thd vs input frequency thd (db) 012345 input frequency (mhz)
ADS850 sbas154c 8 www.ti.com typical characteristics (cont.) at t a = full specified temperature range, v s = +5v, specified input range = 1.5v to 3.5v, differential internal reference input and sampling rate = 10msps after calibratio n, v ref = 2v, 1db input, unless otherwise specified. 400 350 300 250 200 150 100 power dissipation vs temperature power dissipation (mw) 45 5 25 15 55 35 75 95 temperature ( c) 110 100 90 80 70 60 50 40 sinad vs input frequency sinad (db) 012345 input frequency (mhz) 100 90 80 70 60 50 40 sfdr vs input frequency sfdr (db) 012345 input frequency (mhz) 110 100 90 80 70 60 50 40 30 20 10 0 thd vs clock frequency thd (db) 024 6810121416 clock frequency (msps) 110 100 90 80 70 60 50 40 30 20 10 0 sinad vs clock frequency sinad (db) 0246 810121416 clock frequency (msps) 110 100 90 80 70 60 50 40 30 20 10 0 sfdr vs clock frequency sfdr (db) 0 2 4 6 8 10 12 14 16 clock frequency (msps)
ADS850 sbas154c 9 www.ti.com typical characteristics (cont.) at t a = full specified temperature range, v s = +5v, specified input range = 1.5v to 3.5v, differential internal reference input and sampling rate = 10msps after calibratio n, v ref = 2v, 1db input, unless otherwise specified. 110 100 90 80 70 60 50 40 30 swept power sfdr (dbc, dbfs) 60 50 40 dbfs dbc 30 20 10 0 input amplitude (dbfs) f in = 4.8mhz application information driving the analog input the ADS850 allows its analog inputs to be driven either single-ended or differentially. the focus of the following discussion is on the single-ended configuration. calibration procedure the calibration procedure (cal) is started by a positive pulse, with a minimum width of 2 clock cycles. once calibra- tion is initiated, the clock must operate continuously and the power supplies and references must remain stable. the calibration registers are reset on the rising edge of the cal signal. the actual calibration procedure begins at the falling edge of the cal signal. calibration is completed at the end of 32,775 cycles at 10msps, cal = 3.28ms (see timing diagram 3 on page 5). during calibration, the cal_busy signal stays high and the digital output pins of the adc are forced to zero. also, during calibration, the inputs (in and in ) are disabled. when the calibration procedure is complete, the cal_busy goes low. valid data appears at the output seven cycles later or after a total of 32,775 clock cycles. if there are any changes to the clock or the temperature changes more than 20 c, the adc should be re-calibrated to maintain performance. at power-on (see timing diagram 2 on page 5), the adc calibrates itself. the power-on delay, t s , is the time it takes for the reference voltage to settle. once the clock starts, the power-on delay operates for 2 21 clock cycles. bypass capaci- tors should be selected to allow the reference to settle within 200ms. if the system is noisy or external references require a longer settling time, a cal pulse may be required. ac-coupled input configuration see figure 1 for the circuit example of the most common interface configuration for the ADS850. with the v ref pin connected to the sel pin, the full-scale input range is defined to be 2vp-p. this signal is ac-coupled in single-ended form to the ADS850 using the low distortion voltage-feedback amplifier opa642. as is generally necessary for single- supply components, operating the ADS850 with a full-scale input signal swing requires a level-shift of the amplifier s zero-centered analog signal to comply with the adc s input range requirements. using a dc blocking capacitor between the output of the driving amplifier and the converter s input, a simple level-shifting scheme can be implemented. in this configuration, the top and bottom references (reft, refb) provide an output voltage of +3v and +2v, respectively. here, two resistor pairs of 2 2k ? are used to create a common-mode voltage of approximately +2.5v to bias the inputs of the ADS850 (in, in ) to the required dc voltage. an advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. this will keep the distortion performance at its optimum since the signal swing stays centered within the linear region of the op amp and sufficient headroom to the supply rails can be main- tained. consider using the inverting gain configuration to eliminate cmr induced errors of the amplifier. the addition of a small series resistor (r s ) between the output of the op amp and the input of the ADS850 will be beneficial in almost all interface configurations. this will decouple the op amp s output from the capacitive load and avoid gain peaking, which can result in increased noise. for best spurious and distortion performance, the resistor value should be kept below 100 ? . furthermore, the series resistor together with the 100pf capacitor establish a passive low-pass filter, limiting the bandwidth for the wideband noise, thus help improving the snr performance.
ADS850 sbas154c 10 www.ti.com v in 2vp-p 0 +1v 1v r f r in note: r f = r in , g = 1 +v s ADS850 r s 24.9 ? 2k ? 100pf 10 f + +2.5v r 2 r 1 2k ? in in refb (+1v) v ref sel reft 0.1 f 0.1 f opa691 +v s figure 2. dc-coupled, single-ended input configuration with dc-level shift. opa642 v in +v in 0v v in r f 402 ? r g 402 ? ADS850 r s 24.9 ? 2k ? 2k ? 2k ? 2k ? 100pf 0.1 f 0.1 f 2vp-p in in (+2v) refb (+1v) vref sel reft (+3v) +5v 5v +2.5v dc figure 1. ac-coupled input configuration for 2vp-p input swing and common-mode voltage at +2.5v derived from internal top and bottom reference. dc-coupled without level shift in some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS850. in this case, it is only necessary to provide an adequately low source imped- ance to the selected input, in or in . always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. for those applications requiring the driving amplifier to provide a signal amplification, with a gain 3, consider using the decompensated voltage feed- back op amp opa686. dc-coupled with level shift several applications may require that the bandwidth of the signal path include dc, in which case the signal has to be dc- coupled to the adc. in order to accomplish this, the interface circuit has to provide a dc-level shift. the circuit shown in figure 2 employs an op amp, opa681, to sum the ground centered input signal with a required dc offset. the ADS850 typically operates with a +2.5v common-mode voltage, which is established at the center tap of the ladder and connected to the in input of the converter. the opa681 operates in inverting configuration. here resistors r 1 and r 2 set the dc- bias level for the opa691. because of the op amp s noise gain of +2v/v, assuming r f = r in , the dc offset voltage applied to its noninverting input has to be divided down to +1.25v, resulting in a dc output voltage of +2.5v. dc voltage differences between the in and in inputs of the ADS850 effectively will produce an offset, which can be corrected for by adjusting the values of resistors r 1 and r 2 . the bias current of the op amp may also result in an undesired offset. the selection criteria of the appropriate op amp should include the input bias current, output voltage swing, distortion and noise specification. note that in this example the overall signal phase is inverted. to re-establish the original signal polarity, it is always possible to interchange the in and in connections.
ADS850 sbas154c 11 www.ti.com v in in in refb 22 ? 22 ? 100pf 0.1 f 0.1 f r t 100pf 0.1 f reft ADS850 2k ? 2k ? 1:n 0.1 f r g figure 3. transformer-coupled input. single-ended-to-differential configuration (transformer coupled) in order to select the best suited interface circuit for the ADS850, the performance requirements must be known. if an ac-coupled input is needed for a particular application, the next step is to determine the method of applying the signal; either single-ended or differentially. the differential input configuration may provide a noticeable advantage of achiev- ing good sfdr performance based on the fact that in the differential mode, the signal swing can be reduced to half of the swing required for single-ended drive. secondly, by driving the ADS850 differentially, the even-order harmonics will be reduced. figure 3 shows the schematic for the suggested transformer-coupled interface circuit. the resistor across the secondary side (r t ) should be set to get an input impedance match (e.g., r t = n 2 r g ). reference operation integrated into the ADS850 is a bandgap reference circuit including logic that provides either a +1v or +2v reference output, by simply selecting the corresponding pin-strap con- figuration. for more design flexibility, the internal reference can be shut off and an external reference voltage used. table i provides an overview of the possible reference options and pin configurations. input mode range sel v ref refb reft internal 2vp-p v ref sel nc nc internal 4vp-p gnd nc nc nc external 2v < fsr < 4v +v s 1v < fsr < 2v nc nc external (refb reft) 2+v s gnd 1.5v < refb < 2v 2v < reft <3.5v table i. selected reference configuration examples. 800 ? 800 ? refb cm reference driver bandgap and logic reft v ref sel 1v dc resistor network and switches disable switch to adc to adc ADS850 figure 4. equivalent reference circuit. a simple model of the internal reference circuit is shown in figure 4. the internal blocks are a 1v bandgap voltage reference, buffer, the resistive reference ladder, and the drivers for the top and bottom reference which supply the necessary current to the internal nodes. as shown, the output of the buffer appears at the v ref pin. the full-scale input span of the ADS850 is determined by the voltage at v ref , according to equation 1: full-scale input span = 2 v ref (1) note that the current drive capability of this amplifier is limited to about 1ma and should not be used to drive low loads. the programmable reference circuit is controlled by the voltage applied to the select pin (sel). refer to table i for an overview.
ADS850 sbas154c 12 www.ti.com in in reft r 1 cmv r 2 0.1 f 0.1 f ADS850 refb figure 6. alternative circuit to generate common-mode voltage. 3.5v 1.5v in in +2v dc sel v ref 1.24k ? 4.99k ? 0.1 f 10 f +2.5v + ADS850 +5v v in figure 7. external reference, input range 1.5v to 3.5v (2vp-p), single-ended, with +2.5v common- mode voltage. ovr msb under = h over = h figure 8. external logic for decoding under- and over- range condition. ADS850 cm refb 0.1 f 10 f 10 f v ref 0.1 f 0.1 f reft 0.1 f ++ figure 5. recommended reference bypassing scheme. the top reference (reft) and the bottom reference (refb) are brought out mainly for external bypassing. for proper operation with all reference configurations, it is necessary to provide solid bypassing to the reference pins in order to keep the clock feedthrough to a minimum. figure 5 shows the recommended reference decoupling configuration. in addition, the common-mode voltage (cmv) may be used as a reference level to provide the appropriate offset for the driving circuitry. however, care must be taken not to appre- ciably load this node, which is not buffered and has a high impedance. an alternate method of generating a common- mode voltage is given in figure 6. here, two external preci- sion resistors (tolerance 1% or better) are located between the top and bottom reference pins. the common-mode level will appear at the midpoint. the output buffers of the top and bottom reference are designed to supply approximately 2ma of output current. external reference operation depending on the application requirements, it might be advantageous to operate the ADS850 with an external reference. this may improve the dc accuracy if the external reference circuitry is superior in its drift and accuracy. to use the ADS850 with an external reference, the user must disable the internal reference, as shown in figure 7. by connecting the sel pin to +v s , the internal logic will shut down the internal reference. at the same time, the output of the internal reference buffer is disconnected from the v ref pin, which now must be driven with the external reference. note that a similar bypassing scheme should be maintained as described for the internal reference operation. digital inputs and outputs over range (ovr) one feature of the ADS850 is its over range digital output (ovr). this pin can be used to monitor any out-of-range condition, which occurs every time the applied analog input voltage exceeds the input range (set by v ref ). the ovr output is low when the input voltage is within the defined input range. it becomes high when the input voltage is beyond the input range. this is the case when the input voltage is either below the bottom reference voltage or above the top reference voltage. ovr will remain active until the analog input returns to its normal signal range and another conversion is completed. using the msb and its complement in conjunction with ovr a simple clue logic can be built that detects the overrange and underrange conditions, as shown in figure 8. it should be noted that ovr is a digital output which is updated along with the bit information corresponding to the particular sampling incidence of the analog signal. therefore, the ovr data is subject to the same pipeline delay (latency) as the digital data.
ADS850 sbas154c 13 www.ti.com clock input requirements clock jitter is critical to the snr performance of high-speed, high-resolution adcs. it leads to aperture jitter (t a ) which adds noise to the signal being converted. the ADS850 samples the input signal on the rising edge of the clk input. therefore, this edge should have the lowest possible jitter. the jitter noise contribution to total snr is given by the following equation. if this value is near your system require- ments, input clock jitter must be reduced. jittersnr t rms signal tormsnoise in a = ? 20 1 2 log where: in is input signal frequency t a is rms clock jitter particularly in undersampling applications, special consider- ation should be given to clock jitter. the clock input should be treated as an analog input in order to achieve the highest level of performance. any overshoot or undershoot of the clock signal may cause degradation of the performance. when digitizing at high sampling rates, the clock should have a 50% duty cycle (t h = t l ), along with fast rise and fall times of 2ns or less. digital outputs the digital outputs of the ADS850 are designed to be compatible with both high speed ttl and cmos logic families. the driver stage for the digital outputs is supplied through a separate supply pin, vdrv, which is not con- nected to the analog supply pins. by adjusting the voltage on vdrv, the digital output levels will vary respectively. there- fore, it is possible to operate the ADS850 on a +5v analog supply while interfacing the digital outputs to 3v logic. it is recommended to keep the capacitive loading on the data lines as low as possible ( 15pf). larger capacitive loads demand higher charging currents as the outputs are chang- ing. those high current surges can feed back to the analog portion of the ADS850 and influence the performance. if necessary, external buffers or latches may be used which provide the added benefit of isolating the ADS850 from any digital noise activities on the bus coupling back high fre- quency noise. in addition, resistors in series with each data line may help maintain the ac performance of the ADS850. their use depends on the capacitive loading seen by the converter. values in the range of 100 ? to 200 ? will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances, as the output levels change from low to high or high to low. grounding and decoupling proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. multi-layer pc boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. it is recommended that the analog and digital ground pins of the ADS850 be joined together at the ic and be connected only to the analog ground of the system. the ADS850 has analog and digital supply pins, however, the converter should be treated as an analog component and all supply pins should be powered by the analog supply. this will ensure the most consistent results, since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable per- formance. because of the pipeline architecture, the converter also generates high frequency current transients and noise that are fed back into the supply and reference lines. this requires that the supply and reference pins be sufficiently bypassed. figure 9 shows the recommended decoupling scheme for the analog supplies. in most cases, 0.1 f ce- ramic chip capacitors are adequate to keep the impedance low over a wide frequency range. their effectiveness largely depends on the proximity to the individual supply pin. there- fore, they should be located as close to the supply pins as possible. in addition, a larger size bipolar capacitor (1 f to 22 f) should be placed on the pc board in close proximity to the converter circuit. figure 9. recommended bypassing for analog supply pins. +v s 1, 2 gnd ADS850 + 0.1 f 0.1 f +v s 36 gnd 0.1 f +v s 3, 4 2.2 f vdrv 26 0.1 f +5v/+3v +5v note: all gnd pins should be tied together.
package option addendum www.ti.com 17-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ADS850y/250 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS850y ADS850y/250g4 active tqfp pfb 48 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS850y ADS850y/2k active tqfp pfb 48 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS850y (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 17-sep-2015 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS850y/250 tqfp pfb 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 q2 package materials information www.ti.com 16-sep-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS850y/250 tqfp pfb 48 250 210.0 185.0 35.0 package materials information www.ti.com 16-sep-2015 pack materials-page 2
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2015, texas instruments incorporated

▲Up To Search▲

Price & Availability of ADS850

	To Download ADS850 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .